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Title:
DECODING SYSTEM OF VARIABLE LENGTH CODE
Document Type and Number:
Japanese Patent JPS56106471
Kind Code:
A
Abstract:

PURPOSE: To ensure a high-speed decoding, by dividing the decode information into several regions for every code length to store it in an ROM and then selecting a region by the bit number of the signal to be decoded and the color discrimination information.

CONSTITUTION: The code length counter 2 counts the number of bits of the code to be decoded that is supplied to the input terminal DT of the shift register 1. The code is divided into several regions from the result of counting for every code length, and these regions are stored into the ROM11, 12 and 13 each. These ROMs are then addressed based on the number of bits mentioned above and the color discrimination information given from the flip-flop 3 in order to select the prescribed region. Then an access is given to those ROMs for reading with the output of the register 1 used for the address. The original facsimile signal is decoded by the run generating counter 6. Thus no code is required for the information to be decoded, which simplifies the control timing and thus realizes a high-speed decoding.


Inventors:
YAMADA TOSHIAKI
Application Number:
JP836480A
Publication Date:
August 24, 1981
Filing Date:
January 29, 1980
Export Citation:
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Assignee:
RICOH KK
International Classes:
H03M7/46; H04N1/41; H04N1/419; (IPC1-7): H04N1/41



 
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