Title:
DECODING OF WORD OR BIT LINE FOR CMOS SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS6353785
Kind Code:
A
Abstract:
A decoding process and a decoding circuit arrangement for a redundant semiconductor memory is described, wherein the advantages of parallelly selecting non-defective word lines and redundant word lines at a low level are utilized for the writing as well as for the reading current in such a manner that high speed reading and writing is not affected. This is achieved in that the decoder for the redundant word lines consists of a comparator circuit and fuse-controlled switches, and that the input addresses are applied to a conventional address decoder as well as to the comparator circuit. The output of the comparator circuit is directly connected to the input of a first driver circuit for the redundant word line, and furthermore to an OR circuit which is also controlled by a read/write control circuit, and which is connected to the decoder and to a clamp circuit that is directly connected to the input of a second word line driver circuit, and continuously maintains the potential following a deselect signal applied on that level, which requires a minimum of power.
Inventors:
HELWIG KLAUS (DE)
LOHLEIN WOLFDIETER (DE)
TONG MINH H (US)
LOHLEIN WOLFDIETER (DE)
TONG MINH H (US)
Application Number:
JP9551587A
Publication Date:
March 08, 1988
Filing Date:
April 20, 1987
Export Citation:
Assignee:
IBM
International Classes:
G11C11/408; G11C11/401; G11C29/00; G11C29/04; (IPC1-7): G11C11/34; G11C29/00
Domestic Patent References:
| JPS58164100A | 1983-09-28 | |||
| JPS6177946A | 1986-04-21 | |||
| JPS58175196A | 1983-10-14 | |||
| JPS59203299A | 1984-11-17 | |||
| JPS58137192A | 1983-08-15 |
Attorney, Agent or Firm:
Jiro Yamamoto