Title:
電子積層体の深部加工方法および本方法を達成するための装置
Document Type and Number:
Japanese Patent JP2011509834
Kind Code:
A
Abstract:
A method of depth routing an electronic layup comprised of a dielectric sandwiched between a metal layer and a metal substrate which is then laminated. The method involves first positioning a hardened mask so that the mask is interposed between the metal layer and at least one nozzle of a sandblasting machine, the mask having at least one aperture provided therein. Thereafter, the electronic layup is sandblasted through the at least one aperture by way of the sandblasting machine. The force, size and type of abrasive applied by the sandblasting machine are sufficient to erode the metal layer and the dielectric but not the substrate.
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Inventors:
Wee, Kai Hook Francis
Application Number:
JP2010541419A
Publication Date:
March 31, 2011
Filing Date:
December 09, 2008
Export Citation:
Assignee:
Oprent Electronics International Pte Ltd
International Classes:
B24C3/12; B24C1/04; B24C11/00; H05K3/00
Domestic Patent References:
| JPH1050209A | 1998-02-20 | |||
| JPH0639717A | 1994-02-15 | |||
| JPH0430495A | 1992-02-03 | |||
| JP2000022337A | 2000-01-21 | |||
| JP2006140886A | 2006-06-01 | |||
| JP2007015022A | 2007-01-25 | |||
| JP2001274458A | 2001-10-05 |
Foreign References:
| US20070209178A1 | 2007-09-13 |
Attorney, Agent or Firm:
Ikeda adult
Kazuhiro Yamaguchi
Masakazu Noda
Kazuhiro Yamaguchi
Masakazu Noda
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