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Title:
DEFECT CORRECTION CIRCUIT FOR SOLID-STATE IMAGE PICKUP ELEMENT
Document Type and Number:
Japanese Patent JPH0478275
Kind Code:
A
Abstract:

PURPOSE: To attain defect correction processing making a defect not remarkable by providing a position data storage means, a sampling pulse generating means, a delay means and a sample-and-hold means on the correction circuit.

CONSTITUTION: A sampling pulse generating means 3 outputs a sampling pulse SH1 for each output timing of each picture element SNR of a CCD 1 and outputs a sampling pulse SH2 for each output timing of each picture element SBR having a defect based on a position data of a ROM 7. A sample-and-hold means 5 holds an output signal of a solid-state image pickup element by using the pulse SH1 and gives the signal to a delay means 8 and holds the result further by using the pulse SH2 and the delay means 8 gives a delay equivalent to one horizontal scanning period to the signal given to itself. Thus, a signal of a picture element having a defect is replaced into a signal of a picture ele ment having no defect for one preceding horizontal scanning period to apply correction processing.


Inventors:
YAMAMOTO ISAMU
Application Number:
JP18785490A
Publication Date:
March 12, 1992
Filing Date:
July 18, 1990
Export Citation:
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Assignee:
SONY CORP
International Classes:
H04N5/335; H04N5/367; H04N5/372; H04N5/378; (IPC1-7): H04N5/335
Attorney, Agent or Firm:
Akira Koike (2 outside)