PURPOSE: To enable analysis in a short time to determine whether an optional tester pin is defective or not by allowing a defective data for each pin of an IC to be tested to be stored in real time through an input terminal.

CONSTITUTION: An acceptable or defective data to be judged during a test is supplied in real time to a defective data memory 1 from input terminals 11-13. An address buffer 2 sets an address through a data bus 10 to read out a defective data. Then, defective data of all pins read out with the device 1 are applied to one-hand inputs of AND gates 4A-4C. A register block 3 is built in the number corresponding to that of pins of an IC tester. Outputs 17-19 of the register block 3 are applied to the other inputs of the gates 4A-4C. All of the outputs of the gates 4A-4C enter an OR gate 5, an output of which gives '1' only when a specified pin or all the pins are defective. An output terminal 5A leads to a data bus 10 and by checking an address when the '1' is given, it can be learned what ordinal number of patterns is defective.