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Title:
DELAY ADJUSTMENT CIRCUIT, OPTICAL RECEIVER, AND OPTICAL TRANSMISSION SYSTEM
Document Type and Number:
Japanese Patent JP2004112267
Kind Code:
A
Abstract:

To provide a delay adjustment circuit whose size and costs are reduced by changing into an integrated circuit, an optical receiver, and an optical transmission system.

A delay adjustment section 31 has inductances L1, L2 connected between respective load resistors R1, R2 of differential FET1, FET2 and a resistor R3 for bias adjustment each, and FET3, FET4 connected to the inductors L1, L2 in parallel each. A control signal is applied to each gate terminal of the FET3, FET4. In a general differential circuit, when the inductor is connected between the load resistor in the differential FET and a GND, characteristics in a group delay are changed by the inductance components of the inductor, thus adjusting the group delay at a frequency coinciding with an inputted electric signal by utilizing the characteristics for controlling the inductance component of the inductors L1, L2.


Inventors:
OHASHI NAOMI
Application Number:
JP2002271280A
Publication Date:
April 08, 2004
Filing Date:
September 18, 2002
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03K5/13; H04B10/2507; H04B10/2513; (IPC1-7): H03K5/13; H04B10/02; H04B10/18
Attorney, Agent or Firm:
Masataka Nihei