PURPOSE: To form a new analog signal delay circuit which can be used in place for a delay circuit using charge transfer elements, by the application of a switched capacitor.

CONSTITUTION: A plurality of memory cells M1∼Mn in parallel connection between the input terminal IN and the output terminal OUT, are formed with the switched capacitor type analog memory having the input switch SW, output switch SR, and capacitor CS. The switches SW, SR for each memory cell are circulatingly switched with the control pulses WP, RP outputted from the pulse generating circuit 20. The pulse generating circuit 20 can be formed with the shift register which sequentially shifts the clock pulse CP inputted with a prescribed period externally with the clock , and WP1∼WPn as the input switch control pulse WP and RP1∼ RPn as the output switch control pulse RP are produced.