Title:
遅延回路および遅延回路の試験方法
Document Type and Number:
Japanese Patent JP6610216
Kind Code:
B2
Abstract:
A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal; and a logic circuit processes the input signal to the delay line and the delayed signal.
Inventors:
virtue Hiro Nobuyuki
Masazumi Maeda
Masazumi Maeda
Application Number:
JP2015235659A
Publication Date:
November 27, 2019
Filing Date:
December 02, 2015
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K5/133; G01R31/28
Domestic Patent References:
| JP10313238A | ||||
| JP10322178A | ||||
| JP2001344792A | ||||
| JP2003060489A |
Attorney, Agent or Firm:
Atsushi Aoki
Koichi Itsubo
Tsutomu Kono
Tetsuo Miyamoto
Koichi Itsubo
Tsutomu Kono
Tetsuo Miyamoto