PURPOSE: To decrease the number of elements and to reduce a layout area by changing the supplied power voltage of a delay circuit by a switch circuit and changing the delay time in steps.

CONSTITUTION: A delay circuit INV1 consisting of a CMOS inverter is provided together with a waveform shaping circuit SH1 which shapes the waveform of the output signal received from the circuit INV1, and the switch circuits SW1 and SW2 which switch the delay time of the circuit INV1. Then the circuits SW1 and SW2 change the supplied power voltage of the circuit UNV1. At the same time, the power voltage of the circuit INV1 is controlled so that the voltage set by the 85-95% output amplitude of the power voltage is equal to the input threshold voltage of the circuit SH1. Thus a time constant is increased together with increase of the ON resistance of a P-channel transistor of the circuit INV1, and the delay time is set at about 30ns. Then the delay time can be increased by the reduction of the input threshold voltage and the voltage of the circuit INV1.