Title:
DELAY CIRCUIT, TEST DEVICE, CAPACITOR
Document Type and Number:
Japanese Patent JP2002076855
Kind Code:
A
Abstract:
To provide a delay circuit in which delay resolution can be adjusted.
The delay circuit 200 is provided with: a field effect transistor(FET) 210 whose source region and source region are connected to a signal transmission path 206; and an applied voltage control section 220 that controls the voltage applied to the gate electrode of the FET 210. A digital/analog converter may be used in place of the applied voltage control section 220.
Inventors:
OKAYASU TOSHIYUKI
Application Number:
JP2000259446A
Publication Date:
March 15, 2002
Filing Date:
August 29, 2000
Export Citation:
Assignee:
ADVANTEST CORP
International Classes:
G01R31/28; G01R31/30; H03K5/13; H03K5/00; (IPC1-7): H03K5/13; G01R31/28
Domestic Patent References:
| JPH10247842A | 1998-09-14 | |||
| JPH10107598A | 1998-04-24 | |||
| JPH0846496A | 1996-02-16 | |||
| JPH09199999A | 1997-07-31 | |||
| JPH05240919A | 1993-09-21 | |||
| JPH1194905A | 1999-04-09 | |||
| JPH11316260A | 1999-11-16 | |||
| JP2000011692A | 2000-01-14 | |||
| JP2000035461A | 2000-02-02 | |||
| JP2000090693A | 2000-03-31 |
Attorney, Agent or Firm:
Ryuka Akihiro
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