Title:
DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPS55162616
Kind Code:
A
Abstract:
PURPOSE: To make easy the delay for a long time, without deformation of signal waveform, by increasing the circuit branched, through the operations such as branch, hold, synthesis and integration.
CONSTITUTION: The input signal via an impedance converter 11 is time-shared at an analog multiplexer 10 and branched into respective electric circuits. The branched signals are held by a holding capacitor 12 and synthesized with an analog data selector 13. The synthesized signal is input to the integrator 15 via an impedance converter 14, where clock pulse component is integrated with an integration resistor 16 and an integration capacitor 17 and original signal waveform is output.
Inventors:
SOUMA TAKEYOSHI
Application Number:
JP7137779A
Publication Date:
December 18, 1980
Filing Date:
June 05, 1979
Export Citation:
Assignee:
SOUMA TAKEYOSHI
International Classes:
H03H11/26; H03H19/00; (IPC1-7): H03H11/26
Domestic Patent References:
| JP44030043A | ||||
| JPS50126140A | 1975-10-03 |