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Title:
DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPS61198912
Kind Code:
A
Abstract:

PURPOSE: To give a delay time required for a gate circuit or the like to the gate circuit by providing a circuit offering time constant change to the input and/or output of the gate circuit so as to reduce number of circuit elements.

CONSTITUTION: A cathode of a diode D1 is connected to an output side of a resistor R2. A cathode of a diode D3 is connected to an output side of a resistor R6. Then the input leading/trailing time of the gate circuit G2 depends on a product between a resistance of the resistor R2 and series junction capacitance of the diodes D3, D4. The input leading/trailing time of the gate circuit G3 in the setting state of the time constant as above, the delay time from the input to the output is minimized. In changing the output voltage of a variable resistor RV1 toward 0V, the leading time and the trailing time are increased to increase the delay time between the input and output.


Inventors:
KUDO YOICHI
FUJIMIYA JUNICHI
Application Number:
JP3909785A
Publication Date:
September 03, 1986
Filing Date:
February 28, 1985
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03K5/13; (IPC1-7): H03K5/13
Domestic Patent References:
JPS5687923A1981-07-17
JPS5922436A1984-02-04
Attorney, Agent or Firm:
Furuya Fumio



 
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