PURPOSE: To provide a delay control circuit which can facilitate the circuit layout and can prevent the jitter of an output signal by adding two output terminals to each gate circuit to make one of these two terminals touch a multi-input OR circuit and to connect the other terminal to the gate circuit of the next stage.

CONSTITUTION: Each gate circuit 5 contains an input terminal and two output terminals. One of these two output terminals is connected to the input terminal of a multi-input OR circuit 4, and the other output terminal is connected to the input terminal of another circuit 5 of the next stage. The selection signals B0-Bn are inputted to the circuit 5 from a control circuit 1 to select an output terminal that outputs the signal inputted to the circuit 5 as an output signal. A decoder 1 outputs the output signal of a certain circuit 5 to the circuit 4, and other circuits 5 output the signals B0-Bn to output the output signal to each circuit 5 of the next stage. Then an input signal IN is inputted to the input terminal of the circuit 5 of the first stage and an output signal OUT is outputted through the output terminal of the circuit 4. Thus it is possible to facilitate such a layout that can shorten the wiring length of each circuit 5.