PURPOSE: To recover a data clock stably and to identify a data by driving a phase difference detection means with a clock frequency higher than that of the data clock and applying a phase difference signal in 2's complement expression with respect to a data in one preceding time slot to a data identification means.
CONSTITUTION: Analog digital converters 511, 512 sample a data by using an asynchronous clock whose frequency is a multiple of 32 of a frequency of a data clock and convert the data into a digital signal. Multipliers 515-518 multiply the digital signal with a signal in one preceding time slot delayed by delay devices 513, 514 and adders 519, 520 add the result as a phase difference signal and it is sent to data identification devices 521, 522. A clock regenerating circuit 203 recovers the clock in a timing when a most significant bit of the phase difference signal outputted from the adder 520 is inverted and the result is fed to the data identification devices 521, 522. The data identification devices 521, 522 identify each of data of I and Q channels and convert the parallel data into a serial data.
SAITO YOICHI
TANO SATORU
