To provide the delay device that minimizes increase in its circuit scale by eliminating a relative timing difference between an input signal and an output signal after resetting so as to make a delay matching circuit unnecessary for a peripheral system.

A shift register is configured with dummy latches 9, 10 and in connection of the dummy latches 9, 10, a read address generating D latch group 1 and a write address generating D latch group 3 in cascade in the order of a D latch LR1, the dummy latch 10, a D latch LW2,..., a D latch LRn, a D latch LWn-1, the dummy latch 9 and a D latch LWn. Thus, timing of an input signal DI and an output signal DO after reset-input is relatively in matching with each other.