Title:
DELAY INVALIDATION SYSTEM
Document Type and Number:
Japanese Patent JP3437224
Kind Code:
B2
Abstract:
PURPOSE: To invalidate data of a changed entry without affecting reading operation by turning ON a dirty bit at the time of invalidation and invalidating the valid bit of an entry where the dirty bit is set until a next read as to the delay invalidation system which delays the invalidation of a cache and invalidates it.
CONSTITUTION: The system is equipped with the cache 1 which can be accessed from plural buses and has the valid bit 31 and dirty bit 32 and if a conflict to a read of data of another bus is caused when the original data of the cache 1 is altered from one bus for invalidation, the dirty bit 32 is set ON to reset the valid bit 31 of an entry whose dirty bit 32 is ON to an OFF state until next access to the cache 1, thereby performing the invalidation.
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Inventors:
Tsukasa Aoki
Application Number:
JP22412593A
Publication Date:
August 18, 2003
Filing Date:
September 09, 1993
Export Citation:
Assignee:
Pfu corporation
International Classes:
G06F12/08; (IPC1-7): G06F12/08
Domestic Patent References:
| JP5210586A | ||||
| JP2112039A | ||||
| JP6417136A | ||||
| JP1112451A | ||||
| JP2226448A | ||||
| JP721085A |
Attorney, Agent or Firm:
Morihiro Okada