To eliminate the need of circuit simulation at the time of performing the delay calculation of all paths in a logic circuit and to perform highly accurate delay calculation in a short time.
The four variables of input waveform, capacitance and resistance are inputted, the range of a delay table prepared from a frequency, wiring characteristics and the load driving force of a pertinent gate, etc., is decided, a sampling point is decided based on an experimental design method, the circuit simulation is executed and a delay value is obtained. A response surface function(RSF) is generated (S105) from a least squares method based on the delay value and the delay of the sampling point is calculated from the RSF and compared with a simulation result. In the case that an error is equal to or more than an allowable range, the range of obtaining the RSF is changed. In the case that the RSF of respective variable ranges is the error within the allowable range, the preparation of the RSF is ended. The RSF is corrected from measured data and the delay table is generated (S108) from the corrected RSF and stored in a circuit load delay table (S109).
MASUDA HIROO
ITO YUKO
ISOMURA SATORU
YAMASHITA TAKEO
TSUNENO KATSUMI
