PURPOSE: To reduce the number of amplifiers, capacitors and switches by providing a delay circuit comprising the 1st capacitor connected between an output terminal and an inverted input terminal of an amplifier and a switch circuit controlling the storage/transfer of the 3rd capacitor in synchronizing with the alternate connection of one terminal of the 2nd capacitor.
CONSTITUTION: The switches S11, S12 conduct the input/output control of the capacitor C11. The capacitor C11 conducts sampling for a sampled and held output voltage of the pre-stage by using the switches S11, S12. Switches S12, S14 conduct the input/output control of a capacitor C13. The capacitor C11 samples the delayed output voltage subjected to sampling and holding at the pre-stage via the switch S11 at a phase 1. Then the capacitor C11 is connected to an input terminal of an amplifier A11 via the switch S12 at a phase 2, and a voltage corresponding to the sum of the electric charges of the capacitors C11, C12 and C13 appears at an output terminal of the amplifier A11.
AKUTSU EISAKU
MATSUMOTO SHIYUUZOU
