PURPOSE: To obtain a tapped delay line by decreasing the number of quantities of amplifiers, capacitors and switches and connecting in cascade delay circuits advantageous for circuit integration.
CONSTITUTION: The switches S11, S12 perform input/output control of the capacitor C11. After the capacitor C11 samplies an output voltage sampled and held at the pre-stage at a prescribed period by using the switches S11, S12, the capacitor C11 is connected to an input terminal of the amplifier A13. The switches S13, S14 perform the input/output control of the capacitor S12 and the switches S15, S16 perform the input/output control of the capacitor C13 respectively. The capacitors C12 and C13 are connected alternately between an input/ output terminal and ground of the amplifier A13 by the switches S13, S14 and the S15, S16 and this operation is conducted in synchronizing with the transfer period of the C11. The delay circuits like the above are connected in cascade for two stages. Thus, the number of quantities of the amplifiers and capacitors is decreased respectively as the delay circuit to obtain a delay time and also the tapped delay line is constituted.
AKUTSU EISAKU
MATSUMOTO SHIYUUZOU
Next Patent: CONTACT INSERTING DEVICE