Title:
DELAY LOCK LOOP CIRCUIT FOR CLOCK SYNCHRONISM
Document Type and Number:
Japanese Patent JPH04364609
Kind Code:
A
Abstract:
PURPOSE: To solve problems, such as instability in case of acquiring synchronism and a long start time after resetting. CONSTITUTION: When a clock signal VOUT is distributed among a large number of loads and a phase detector 21 detects phase difference between a clock signal and a reference signal REF, a capacitor C in a low-pass filter is charged in time consistent with the reference signal, so that a delay circuit 40 can be provided at a loop circuit for sending back a control voltage VCTRL to a veritable delay line 20 for passing the clock signal before distribution and a delayed reference signal 10 can be generated by delaying the reference signal timewise. Further, the phase detector 21 detects a phase difference between the reference signal and the clock signal, detects the phase difference between the delayed reference signal, and the clock signal and generates plural output voltages VC and VC'. By providing a logic circuit 30 and regulating the control voltage, a variable delay line is driven.
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Inventors:
EDOWAADO EI RITSUCHIRII
Application Number:
JP33353891A
Publication Date:
December 17, 1992
Filing Date:
December 17, 1991
Export Citation:
Assignee:
XEROX CORP
International Classes:
G06F1/10; H03K5/13; H03L7/00; H03L7/06; H03L7/081; (IPC1-7): G06F1/10; H03L7/00; H03L7/06
Attorney, Agent or Firm:
Minoru Nakamura (7 outside)