Title:
DELAY LOCKED CIRCUIT
Document Type and Number:
Japanese Patent JP3233893
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a delay locked circuit without causing the problem that no accurate locking is made due to the occurrence of internal step jitter.
SOLUTION: This circuit is made up of a delay controller 2 that delays an input clock signal RCLK by a prescribed time, compares a phase of the delayed input clock signal RCLK with a phase of an internal clock signal ICLK, delays the internal clock signal ICLK by a prescribed time, compares the phase of the delayed internal clock signal ICLK with the phase of the input clock signal RCLK and provides an output of a control signal to decide the degree of delay of the input clock signal RCLK and up of a variable delay device 3 that delays the input clock signal RCLK with a control signal of the delay controller 2 by a prescribed time to output the internal clock signal ICLK.
Inventors:
Sun light
Application Number:
JP63398A
Publication Date:
December 04, 2001
Filing Date:
January 06, 1998
Export Citation:
Assignee:
ELGE SEMICON Company Limited
International Classes:
H03K5/135; G06F1/10; G11C11/407; G11C11/4076; H03K5/12; H03K5/13; H03L7/00; (IPC1-7): H03K5/135; H03L7/00
Domestic Patent References:
| JP3289813A | ||||
| JP1305614A | ||||
| JP50156969A | ||||
| JP56169931A | ||||
| JP6164386A |
Attorney, Agent or Firm:
Hajime Tsukuni
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