To provide a delay locked loop in which jitter is reduced during a high frequency operation, generation of a hole during the initialization operation of the delay locked loop is suppressed and a reset command signal normally functions.
The delay locked loop of a semiconductor storage element including a delay line section and a replica model, is provided with: a comparator enable signal generating section 303 that outputs a comparator enable signal (compen) in which a reset command signal is extended for a prescribed time; and a semi-lock detecting section 304 which outputs a semi-lock command signal (semilock) that is controlled by the logical state of the comparator enable signal. When the comparator enable signal is in a first logical state, a phase comparison section 305 compares the phase of a rise clock being inputted to the phase comparison section 305 with the phase of a feedback clock and outputs a signal, that is not related to the comparison result, under the control of the (semilock) command signal.
| JP3461237 | COMPUTER SYSTEM AND ITS CLOCK CONTROL METHOD |
| JPS6468016 | CLOCK PULSE GENERATING CIRCUIT |
Kakehi Yuro
Kimio Matsumoto