デシメートされた係数（ｄｅｃｉｍａｔｅｄｃｏｅｆｆｉｃｉｅｎｔｓ）のフィルタリングを実行する他の回路またはアクティヴ雑音相殺回路における遅延技術

Title:

Document Type and Number:

Japanese Patent JP5897739

Kind Code:

B2

Abstract:

This disclosure describes circuit configurations that may be used for active noise cancellation in the digital domain. In particular, this disclosure proposes the use a down sample unit and an up sample unit, rather than memory-based delay circuits, to achieve one or more desired delays in digital adaptive noise cancellation circuits or other circuits that use delay for signal processing. The delay achieved by the down sample unit and the up sample unit may be tunable so as to allow flexibility in producing the necessary delay for different active noise cancellation circuit configurations. Many different adaptive noise cancellation circuit configurations are discussed, and the techniques may also be useful for other types of circuits, such as low-latency equalization circuits.

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Inventors:

Kwaklung Chan
Len Li
Hyun Jin Park

Application Number:

JP2015000526A

Publication Date:

March 30, 2016

Filing Date:

January 05, 2015

Export Citation:

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Assignee:

QUALCOMM INCORPORATED

International Classes:

H03H17/00; G10K11/178; H03H17/02; H03H17/08; H04B15/00

Domestic Patent References:

JP3006919A
JP10283003A
JP64047117A
JP2005128175A
JP2001282254A
JP2003037641A
JP2006295501A
JP4339500A
JP7064582A
JP2009094763A

Foreign References:

WO2007095664A1
US20040049376
EP1970902A1
EP2101506A1

Attorney, Agent or Firm:

Kurata Masatoshi
Yoshihiro Fukuhara
Morisezo Iseki
Okumura Motohiro

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