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Patent Searching and Data


Title:
DELAY TIME MEASURING CIRCUIT
Document Type and Number:
Japanese Patent JPH10300821
Kind Code:
A
Abstract:

To provide such a delay time measuring circuit as being capable of distinguishing rising/trailing transmission delay times for a logical circuit element to highly precisely measure them with a small circuit scale.

This circuit has a reverse signal addition circuit 13 to which an outside input terminal 1N and a measuring control signal CONT are connected, a selector part 11 which contains a selector 7 to input selective signals S1, S2 and AND circuits 8, 9, 10 and a measuring circuit part 6 which contains a reference line 3 and the signal passages 4, 5 to longitudinally connect plural measured circuits 1, 2 thereto, a multiplexer 12 to which output signals and selective signals S1, S2 from these signal passages 4, 5 and the reference line 3 are connected and a dividing circuit 15 to which the measuring control signal CONT and the output of the multiplexer 12 are connected. A feedback loop formed with the reverse signal addition circuit 13, the selector part 11, the measuring circuit part 6 and the multiplexer 12 is used to generate a measuring signal.


Inventors:
UMEZAWA MASAYOSHI
Application Number:
JP10928997A
Publication Date:
November 13, 1998
Filing Date:
April 25, 1997
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
H01L21/66; G01R31/28; (IPC1-7): G01R31/28; H01L21/66
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)