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Title:
DELTA MODULATOR
Document Type and Number:
Japanese Patent JPS6133033
Kind Code:
A
Abstract:

PURPOSE: To prevent assuredly idle noise at a no-signal mode by outputting a delta-modulated output code train for a fixed period of time when ≥3 pieces of same codes are detected out of said code train and otherwise outputting the alternating codes.

CONSTITUTION: In an input mode of a sound signal (x), ≥3 pieces of same codes od 1 or 0 are produced continuously within a short period of time for the output signal Z of a delta modulator 10. These same codes are detected by a code monitor means 21 and supplied to a retrigger type monostable circuit 23 of a code output converting means 22. The semi-stable holding time of the circuit 23 is set longer than the maximum time interval of a code train. Thus the means 21 is retriggered and a semi-stable state is kept a sound input mode. A switch 24 is connected to A. A sampling pulse 25 samples the signal Z with a sampling pulse SP and outputs the code output signal Z' having the same form as the signal Z. The signal Z is not outputted to a no-signal mode and no detection output of the means 21 is obtained with no retrigger of the circuit 23 secured. Then the switch 24 is connected to B, and the circuit 25 outputs an alternating signal Z' of a cycle double as much as the sampling cycle. Thus the idle noise is prevented.


Inventors:
SAKAKIBARA TAKASHI
Application Number:
JP15399984A
Publication Date:
February 15, 1986
Filing Date:
July 26, 1984
Export Citation:
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Assignee:
PIONEER ELECTRONIC CORP
International Classes:
H04B14/06; (IPC1-7): H04B14/06
Domestic Patent References:
JPS5140064A1976-04-03
JPS56119528A1981-09-19
Attorney, Agent or Firm:
Hideo Takino