Title:
ΔΣ形ＡＤ変換器
Document Type and Number:
Japanese Patent JP6686717
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To inexpensively implement accurate AD conversion without using an expensive high-frequency PLL circuit in a power converter or relay requiring AD conversion of voltage, current, etc.SOLUTION: Synchronization of a PWM carrier with decimeter operation timing is implemented by using reference clock oscillators having frequencies slightly differing from each other. A synchronization correction function is implemented by minutely changing a frequency division ratio selection signal Msel by adjusting a decimation ratio M inside a modulation filter. As a synchronization reference signal, there are two types of signals of a synchronization timing signal Ts(m) and a carrier peak timing Tc(m).SELECTED DRAWING: Figure 1
Inventors:
Yasuhiro Yamamoto
Takiguchi Shoji
Takiguchi Shoji
Application Number:
JP2016116953A
Publication Date:
April 22, 2020
Filing Date:
June 13, 2016
Export Citation:
Assignee:
KABUSHIKI KAISHA MEIDENSHA
International Classes:
H02M7/48; H03K7/08; H03M3/02
Domestic Patent References:
| JP2013198229A | ||||
| JP201358894A | ||||
| JP1042569A |
Attorney, Agent or Firm:
Hiromichi Kobayashi
Uzawa Hidehisa
Uzawa Hidehisa