PURPOSE: To enable accurate data demodulation by reducing the readout error even if demodulated clock pulse fluctuates slightly, by providing a means to read out the edge detecting pulse extending the width of detection window based on a demodulated clock pulse.

CONSTITUTION: Two FF circuits are provided at a "101" pattern detecting circuit of a demodulation circuit using a PLL circuit 2 to obtain the "101" detection output and a means extending the width detection window based on the demodulated clock pulse is provided. For example, an edge detection pulse (c) via an inverter 8, and a demodulation clock pulse (d) via an inverter 9 are inputted to FF circuits 6, 7 and "101" detection output (f) is obtained from an AND gate 10 via the measurement of signal invertion interval and pulse count processing and the pulse width of the output (k) of an AND gate 12 is extended to required width of detection window based on a demodulated clock pulse.