PURPOSE: To demodulate a reception signal with high linearity by setting up the gate width of a field effect transistor(FET) constituting the source follower circuit of the final stage so that an output impedance is set up smaller than the impedance of a load circuit connected to the source follower circuit.

CONSTITUTION: The FET Q12 constituting the source follower circuit of the final stage goes to the load of a source follower circuit based upon FET Q11, and since the input impedance of the FET Q12 is high impedance, the load of the FET Q11 goes to high impedance and the voltage gain of the FET Q11 is almost '1'. Since the gate width of the FET Q12 is set up so as to be smaller than the impedance of the load circuit connected to an output terminal 12, the load impedance of the FET Q12 is also increased and the voltage gain of the FET Q12 goes to almost '1'. Thereby, signal amplitude inputted to respective source follower circuits is reduced. Thus, a reception signal can be demodulated with high linearity.