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Patent Searching and Data


Title:
DEMODULATOR, DEMODULATION METHOD AND TERMINAL EQUIPMENT
Document Type and Number:
Japanese Patent JP2002016578
Kind Code:
A
Abstract:

To provide a demodulator that can adaptively control arithmetic accuracy of a digital signal processing section, on the basis of a propagation state of an orthogonal frequency division multiplex signal for reducing the power consumption.

A valid OFDM symbol is extracted from an input data memory 1, an FFT 2 applies OFDM demodulation to the symbol, an equalizer 3 applies channel estimation/equalization to the output of the FFT 2, and the result is fed to an error correction coding decoding device 4 and an S/N measurement section 5. The S/N measurement section 5 calculates an S/N, on the basis of the signal supplied from the equalizer 3, while the error correction coding decoding device 4 calculates metric processing on the basis of the signal supplied from the equalizer 3. An integrator 6 integrates the metric output from the error correction coding decoding device 4. An arithmetic bit word length setting circuit 7 supplies a control signal to set an optimum arithmetic bit word length to each processing section, on the basis of the supplied S/N and metric integral value.


Inventors:
Honda, Makoto
Fukuda, Kunio
Application Number:
JP2000000194716
Publication Date:
January 18, 2002
Filing Date:
June 28, 2000
Export Citation:
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Assignee:
SONY CORP
SONY TEKTRONIX CORP
International Classes:
H03M13/01; H03M13/41; H04J11/00; H04L25/02; H03M13/00; H04J11/00; H04L25/02; (IPC1-7): H04J11/00; H03M13/01; H03M13/41; H04L25/02