Title:
DEMODULATOR
Document Type and Number:
Japanese Patent JP2658877
Kind Code:
B2
Abstract:
PURPOSE: To provide the demodulator which can efficiently demonstrate the equalizing ability of a decision feedback type equalizer and can perform a clock pull-in operation in a short time at the same degree as conventional even when an extracted clock component is reduced by a notch frequency caused by phasing.
CONSTITUTION: A/D converters 10 and 11 convert demodulated base band signals to digital signals based on input clock signals. A frame synchronization detector 26 detects frame synchronization based on the output data of a decision feedback type equalizer 13. A clock synchronizing circuit 25 extracts clock signal components from the demodulated base band signals and when inputting a signal at the time of detecting the frame synchronization with the frame synchronization detector 26, a clock signal phase-locked with the extracted clock component is generated but when inputting a signal at the time of detecting no frame synchronization, a clock signal at the frequency corresponding to the extracted clock signal component is generated.
Inventors:
KOBAYASHI HIDEYUKI
Application Number:
JP13838794A
Publication Date:
September 30, 1997
Filing Date:
May 26, 1994
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H03H17/00; H03H15/00; H03H21/00; H04B3/04; H04B7/005; H04L7/033; H04L27/01; H04L27/22; (IPC1-7): H04L27/22; H04B7/005; H04L7/033; H04L27/01
Attorney, Agent or Firm:
松浦 兼行
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