Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH0750096
Kind Code:
A
Abstract:
PURPOSE: To shorten the time for verifying the erasure of a flash memory.
CONSTITUTION: A dummy cell DC showing a similar characteristic of the erasing distribution to that of an a nonvolatile memory cell MC is provided corresponding to at least one column or one row of a memory array 1. The dummy cell DC is erased at one time together with the nonvolatile memory cell MC. Data of the dummy cell DC is read out instead of reading the nonvolatile memory cell MC to confirm the erasure. Accordingly, by confirming the read data of the dummy cell DC, the number of bites to carry out the verification is reduced and the time necessary for the verification of the erasure is shortened.
Inventors:
IEGI TOMOMASA
KOBAYASHI KAZUO
KOBAYASHI KAZUO
Application Number:
JP19472693A
Publication Date:
February 21, 1995
Filing Date:
August 05, 1993
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G11C17/00; G11C16/02; G11C16/04; G11C16/06; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): G11C16/06; H01L27/115; H01L21/8247; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)
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