Title:
【発明の名称】演算増幅器のための平衡型高速差動入力段
Document Type and Number:
Japanese Patent JPH08505032
Kind Code:
A
Abstract:
A differential input circuit has two halves, each half includes a differential input voltage terminal with a first emitter follower having its base terminal connected to the input terminal, having a collector terminal connected to a first voltage terminal, an emitter terminal connected to a first terminal of an emitter resistor. A second emitter follower is provided having has its base terminal connected to the first differential input terminal, having a collector terminal connected to the first voltage terminal, and having an emitter terminal. A diode-connected transistor is provided having an emitter terminal connected to the emitter terminal of the second emitter follower, having its base and collector terminals connected together. A current source is provided having an output terminal connected to the base and collector terminals of the first diode-connected transistor, and having an input terminal connected to a second voltage terminal. An output drive transistor is provided having its base terminal connected to the base and collector terminals of the first diode-connected transistor, having its emitter terminal connected to the first terminal of the emitter resistor, and having a collector terminal for providing a differential output current.
Inventors:
Moravege, Ferhood
Application Number:
JP51175595A
Publication Date:
May 28, 1996
Filing Date:
July 20, 1994
Export Citation:
Assignee:
National Semiconductor Corporation
International Classes:
H03F3/343; H03F3/45; (IPC1-7): H03F3/45; H03F3/343
Attorney, Agent or Firm:
Kyozo Yuasa (6 people outside)