Title:
【発明の名称】バイアス電流制御回路
Document Type and Number:
Japanese Patent JP2689708
Kind Code:
B2
Abstract:
This invention relates to a bias current control circuit which drives a power MOS transistor. Since the power MOS transistor has a large capacitance which is formed between a gate and a channel, it is needed to provide a circuit which is able to sufficiently supply a drive current to the gate. Such a circuit increases a consumption current because the circuit has to always flow the current to drive the gate. This invention provides a circuit which cut the consumption current in the circuit when the transistor is not driven, and increases a consumption current in the circuit in order to keep a gate current when the transistor is driven.
Inventors:
Kiyoshi Kase
Application Number:
JP24625390A
Publication Date:
December 10, 1997
Filing Date:
September 18, 1990
Export Citation:
Assignee:
Nippon Motorola Co., Ltd.
International Classes:
G05F1/565; H03F1/02; H03F3/45; H03K17/04; H03K17/042; H03K19/0175; (IPC1-7): H03K17/04; H03K19/0175
Domestic Patent References:
| JP1227520A | ||||
| JP5919432A |
Attorney, Agent or Firm:
Masanori Honjo (1 person outside)