Title:
【発明の名称】高性能・低電力オンチップ相互配線用の差動・混スイング型トライステートドライバ回路
Document Type and Number:
Japanese Patent JP2003526956
Kind Code:
A
Abstract:
A driver to provide low voltage swings on a bus with fast switching times, the driver comprising two pairs of pullup and pulldown nMOSFETs, each pair operated in complementary fashion to each other, each pair with a high voltage rail at a smaller voltage than the data input logic HIGH voltage, and where each substrate of the nMOSFETs are biased so as to reduce their threshold voltages.
Inventors:
Krishna Mercy, Ram Kumar
De Vivec
Saumyanus, Krishna Mercy
De Vivec
Saumyanus, Krishna Mercy
Application Number:
JP2000527024A
Publication Date:
September 09, 2003
Filing Date:
November 24, 1998
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
H03K19/0175; H03K19/017; H03K19/0185; (IPC1-7): H03K19/0175
Attorney, Agent or Firm:
Masaki Yamakawa