Title:
【発明の名称】半導体記憶装置の冗長回路
Document Type and Number:
Japanese Patent JP2575919
Kind Code:
B2
Abstract:
A semiconductor memory device having a redundancy circuit for remedying defective columns caused during manufacture, includes a plurality of spare memory cells for storing binary data, spare bit lines connected to the outputs of the spare memory cells, respectively, and each having two or more columns, a spare gate circuit for controlling the outputs of the spare bit lines, a circuit having storage sections for storing addresses of the defective columns, for generating a spare gate selection signal in response to one of the addresses of the defective columns and selecting a spare gate, and a circuit for prohibiting all the outputs from a column decoder in response to the spare gate selection signal. The defective columns are remedied in units of columns whose number is smaller than that of columns of the spare bit lines.
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Inventors:
OGIWARA MASAKI
Application Number:
JP7281890A
Publication Date:
January 29, 1997
Filing Date:
March 22, 1990
Export Citation:
Assignee:
TOSHIBA KK
TOSHIBA MAIKUROEREKUTORONIKUSU KK
TOSHIBA MAIKUROEREKUTORONIKUSU KK
International Classes:
G11C11/401; G11C29/00; G11C29/04; G11C29/24; G11C29/44; H01L21/82; H01L27/10; (IPC1-7): G11C29/00
Domestic Patent References:
| JP60103469A | ||||
| JP6242395A | ||||
| JP63160095A | ||||
| JP6240700A |
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)