Title:
【発明の名称】1ビットフォーマットのデータを処理するための回路、装置および方法
Document Type and Number:
Japanese Patent JP2002534891
Kind Code:
A
Abstract:
Digital-to-analog conversion circuitry 100 is shown including a path for processing data in a 1-bit format. First portion of an analog finite impulse response filter 300 includes pre-selected number of delay elements 301 for receiving stream of data in the 1-bit format and outputting a plurality of signals in response. A switched capacitor digital-to-analog converter 106 forms a second portion of the finite impulse response filter 301 and has a plurality of elements each receiving one of the plurality of signals as selected to effectuate a set of filter coefficients, converter 106 summing the plurality of signals and outputting an analog data stream.
Inventors:
Gon, Sue-Mei
Alexander,mark
Paulus, John, James
Garras, Eric
Hester, Dylan
Alexander,mark
Paulus, John, James
Garras, Eric
Hester, Dylan
Application Number:
JP2000592946A
Publication Date:
October 15, 2002
Filing Date:
December 29, 1999
Export Citation:
Assignee:
Shirasu Logic, Inc.
International Classes:
H03H19/00; H03M3/02; H03M3/04; H03M1/66; H03M1/06; (IPC1-7): H03M3/02; H03H19/00; H03M1/66
Attorney, Agent or Firm:
Akira Asamura (3 outside)