Title:
【発明の名称】負荷電流を自動的に減少させる回路配列
Document Type and Number:
Japanese Patent JPH08504319
Kind Code:
A
Abstract:
PCT No. PCT/EP93/03137 Sec. 371 Date May 17, 1995 Sec. 102(e) Date May 17, 1995 PCT Filed Nov. 9, 1993 PCT Pub. No. WO94/14229 PCT Pub. Date Jun. 23, 1994A circuit arrangement for automatically decreasing the load current includes a series arrangement formed by a load and a first electronic switching device and connected to a DC source of power. The first switching device is driven by a driver. The circuit further includes a control circuit controlling the driver. The control circuit is adapted to be initiated by a second electronic switching device, so that the second electronic switching device connects the first terminal of a capacitor and of a first resistor as well as the base of a transistor to one pole of the DC source of power, with the main current path of the transistor being between the input of the driver and the other pole of the DC source of power. The second terminal of the capacitor and of the first resistor is coupled to the other pole of the DC source, and the end of the first electronic switching device connected to the load is coupled to the second terminal of the capacitor through a feedback resistor.
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Inventors:
Lang Gerhard
Application Number:
JP51370994A
Publication Date:
May 07, 1996
Filing Date:
November 09, 1993
Export Citation:
Assignee:
BRAUN AG (DE)
International Classes:
G05F1/59; H02J1/00; H02H7/18; H02J7/00; H02J9/00; H02M3/10; H02M3/156; H02P7/28; (IPC1-7): H02J1/00
Attorney, Agent or Firm:
Hiroo Suzuki