Title:
【発明の名称】半導体記憶装置の製造方法および半導体記憶装置
Document Type and Number:
Japanese Patent JP3011152
Kind Code:
B2
Abstract:
A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.
Inventors:
Kenji Hibino
Masao Kunigami
Kazuyuki Yamazaki
Tetsuji Togami
Hironori Sakamoto
Kiyokazu Hashimoto
Masao Kunigami
Kazuyuki Yamazaki
Tetsuji Togami
Hironori Sakamoto
Kiyokazu Hashimoto
Application Number:
JP26905397A
Publication Date:
February 21, 2000
Filing Date:
October 01, 1997
Export Citation:
Assignee:
NEC
International Classes:
G11C11/56; G11C17/08; H01L21/8246; H01L27/10; H01L27/112; (IPC1-7): H01L21/8246; G11C17/08; H01L27/10; H01L27/112
Domestic Patent References:
| JP955094A | ||||
| JP9116028A |
Attorney, Agent or Firm:
Tadashi Wakabayashi (4 others)