Title:
【発明の名称】マルチデジタル信号処理を実行するための選択的に構成可能な集積回路デバイス
Document Type and Number:
Japanese Patent JPH07501413
Kind Code:
A
Abstract:
A single integrated circuit device is disclosed that is capable of selectively functioning in real time as either a sequential matrix multiplier, a parallel matrix multiplier, a convolver or a finite input response FIR filter in order to process image data. A core group of multipliers is used to provide the basic multiplication operation that is common to each of the desired image processing functions. Input data router unit, coefficient router units and an output data router unit are responsive to mode selection control signals, supplied to a mode selection port, to route the appropriate input data and coefficients to the core group of multipliers and to route the output of the adders to the correct output port(s) for each of the desired processing functions.
Inventors:
Doruna Lionel Joseph
Mirch james roger
Kenie Timothy Joseph
Mirch james roger
Kenie Timothy Joseph
Application Number:
JP50812593A
Publication Date:
February 09, 1995
Filing Date:
September 07, 1993
Export Citation:
Assignee:
Eastman Kodak Company
International Classes:
H04N9/67; G06F17/16; G06T1/00; G06T1/20; G06T5/00; G06T5/20; H03H17/02; (IPC1-7): G06F17/16; G06T1/00; G06T5/00; G06T5/20; H03H17/02; H04N9/67
Attorney, Agent or Firm:
Kenji Yoshida (2 outside)