Title:
DESIGN DEVICE, DESIGN METHOD, AND DESIGN PROGRAM
Document Type and Number:
Japanese Patent JP2015225432
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To efficiently implement logic synthesis and place/route by inhibiting an occurrence of wiring congestion and increase in a layout area.SOLUTION: The design device generates a logic cone 400, and calculates an area ratio of a triangle Im, with a logic cell on an m-th stage between an input stage and an output stage, and input sides FF380 at both ends of input stages connected to the input thereof defined as vertices, to a triangle On, with output sides FF300 of the output stage and logic cells at both ends of the m-th stage connected to the input thereof defined as vertices. The design device sets an input stage-side first logic cone part and an output stage-side second logic cone part from the m-th stage where the calculated area ratio turns out a prescribed ratio, to a logic synthesis unit, and implements the logic synthesis using the set logic synthesis unit.
Inventors:
ARAKAWA TOSHIO
YAMAGATA YOSHINORI
YAMAGATA YOSHINORI
Application Number:
JP2014108959A
Publication Date:
December 14, 2015
Filing Date:
May 27, 2014
Export Citation:
Assignee:
SOCIONEXT INC
International Classes:
G06F17/50
Attorney, Agent or Firm:
Takeshi Hattori