To provide a design support system, a design method, a design support program and a manufacturing method of a semiconductor integrated circuit, with which occurrence of a design pattern that is a main cause of a circuit defect and is difficult to be lithography-processed can be suppressed, dispersion due to manufacture fluctuation is suppressed and yield can be improved.
The system is provided with a data storage device 3 storing information on a defective pattern which is collected through a computer network 9 and is difficult to be lithography-processed, a layout means 10 which defines a plurality of regions in a chip and decides a layout of the chip, a manufacture easiness analysis means 20 reading information of the defective pattern and a decision result of the layout, calculating occurrence frequency of the defective pattern at every region and analyzing manufacture easiness of the layout by occurrence frequency and a layout correcting means 15 which selectively extracts the region whose occurrence frequency is not less than a prescribed value and correcting arrangement of cells and wiring in the region.
| JP2003162041A | 2003-06-06 | |||
| JP2005039001A | 2005-02-10 | |||
| JP2004191297A | 2004-07-08 |
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu