Title:
DESIGN VERIFICATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT TOOL
Document Type and Number:
Japanese Patent JP2003248704
Kind Code:
A
Abstract:
To easily verity the restriction for burn-in examination of a wafer level in a design stage of a single chip.
This method includes a floor plan process 100, a process 101 for placing the layouts same as that of the verified chip, in adjacent to upper, lower, left and right parts of the layout of the verified chip, a process 103 for reading a design tool by the restriction of the wafer level burn examination, and a process 104 for verifying a design rule.
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Inventors:
YAMANAKA MITSUE
MOGI ISAO
MOGI ISAO
Application Number:
JP2002049852A
Publication Date:
September 05, 2003
Filing Date:
February 26, 2002
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50; H01L21/82
Attorney, Agent or Firm:
Shohei Oguri (4 outside)