PURPOSE: To prevent an erroneous clock signal inputting to a device by selecting one transmitting signal out of a 1st and 2nd AND circuits to output by a selection circuit.

CONSTITUTION: The plural 1st time limit circuits 1, 2 which are respectively furnished with different times of the time limit operate in response to the clock signal at the time when any one among the clock signals having plural kinds of cycle is inputted. These circuits 1, 2 are utilized, and further a time limit circuit 11 to monitor the condition of output signal from the circuit 2, AND circuit 31 to take a logical product of the output signal from circuit 1 and the output signal from circuit 11, inversion circuit 21 to invert a logical level of the output signal from circuit 11, and AND circuit 32 to take a logical product of the output signal from circuit 2 and the output signal from circuit 21 are additionally connected. Then, either one of the output signals from the circuits 31 and 32 is selected by the selection circuit 5 in accordance with the selection signal and sent out as the output signal.