PURPOSE: To detect the quantity of advance and lag in phase, by detecting a phase difference between AC voltage and current on a basis of a DC voltage level obtained by averaging and synthesizing the added value of advancing phase-side and lagging phase-side sample holding means in DC.

CONSTITUTION: Respective zero crossing times of a voltage and a current are detected by a detected data operating circuit 10, polarity inverters NOTi, and NAND gates NANDi to generate prescribed logical conditions, and information concerning the time difference of zero crossing are sampled on a basis of the logical condition output by advancing phase-side sample holding circuits 20I and 20II, and output states are shifted periodically from each other by the phase difference of a half cycle, and lagging phase data are sampled similarly by lagging phase-side sample holding circuits 20III and 20IV. These outputs are added and are averaged in DC and are synthesized to attain the DC voltage level, and the phase difference between AC voltage and current is detected on a basis of this DC voltage level.