PURPOSE: To improve computation accuracy and detection responsiveness by using a first-in-first-out type memory, outputting data of 90° delay from input and making vector synthesis.

CONSTITUTION: A clock generating circuit 11 generates the clock pulse which is synchronized with an input AC current signal I to a 1st phase shifting circuit 10 and is integer multiple the frequency of the signal I. The signal I is converted and is stored in a memory 13 to shift the contents in synchronization with the clock signal from the circuit 11. After the clock signal corresponding to 90° of the basic wave of the input AC is counted, the data is outputted in accordance with order of later input. The output signal has 90° phase difference from the input signal and forms a 2-phase AC signal. The two AC signals are passed through an absolute value computing circuit 16 and a filter 17, by which the absolute value is obtd. The AC voltage signal V from a power supply 21 is passed through the 2nd phase circuit 20, by which the 2-phase AC voltage signal is similarly obtd. The current signal from the circuit 10 is inputted to a vector rotating circuit 26, by which a sine value and cosine value are obtd. The accuracy of the result of the computation is thus improved and the responsiveness of the detection is greatly improved.