To detect the excess pulse of a clock signal.

An FP (0-system) extra-pulse detection circuit 30-0 loads 0 to a full frame counter by a 0-system frame pulse FP0 and count-operates the rising edge of a clock CLK0. When the value becomes 1023 and a 0-system frame pulse is 'H' and an 1023 detection signal is 'L', an excess pulse detection signal is outputted. A CLK (1-system) excess pulse detection circuit 30-1 detects the extra-pulse of FP1. When disconnection and the excess pulse are detected at the 0-system clock CLK0, the 1-system clock CLK1, the 0-frame pulse FP0 and a 1-system frame pulse FP1, a system selecting control processing/alarm transfer processing circuit 31 outputs a selection signal SEL in order to switch to a normal system. A clock selector 4 and a frame pulse selector 5 select a system. A counter 6 counts at the selected system to generate various timing signal.