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Title:
DETECTION CIRCUIT OF SIGNAL INTENSITY
Document Type and Number:
Japanese Patent JPS5480603
Kind Code:
A
Abstract:

PURPOSE: To increase the detection sensitivity without giving effect to the operation of the amplitude limit type amplifying stage, by making greater the input impedance and constituting the signal intensifier detector with the differential comparison circuit, in the circuit detecting the intensity of reception signal.

CONSTITUTION: The signal intensity detector is constituted by the connection of a plurality of stages of differential comparators consising of transistors 60 and 61 and the amplitude limit amplifier is formed with a plurality of stage connections of the differential amplifier of transistors 32 and 33 and the emitter follower transistor 39. At no signal, since only the first transistor 1 constituting the differential comparator is conducted, no signal intensity signal output is picked up from the current Miller circuit (consisting of diode 29 and transistor 31). When signal input is present to the amplitude limit amplifier, current is flowed to the second transistor of the differential comparator and the signal intensity signal is obtained from the current Miller circuit mentioned above.


Inventors:
ISHII HIDEKAZU
Application Number:
JP14837277A
Publication Date:
June 27, 1979
Filing Date:
December 09, 1977
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G01R29/08; H03J3/14; H04B1/16; (IPC1-7): H04B1/16
Other References:
PLESSEY SEMICONDUCTORS INTEGRATED CIRCUIT DATABOOK=1973