PURPOSE: To simplify the constitution of a bit error rate monitoring circuit by providing additionally a parity bit inserting circuit to a transmission logical section of a time division multiplex communication device for adding a parity bit to a transmission main signal.

CONSTITUTION: The transmission logical section of the time division multiplex communication device is provided additionally with a parity bit inserting circuit 100, a binary counter 11 of the circuit 100 counts a transmitted main signal (a), and the parity bits (b) and c(=b') being an odd or an even number are outputted. Further, a parity bit auxiliary signal (d) is outputted from a timing generating circuit 12 and added to one side of an AND gate 13. The parity bits (b and C) outputted from the counter 11 are applied to the other side of the gate 13 via a jumper 15 to output a parity bit signal (e) in response to the auxiliary signal (d). Further, the bit signal (e) is applied to an OR gate 14 to add the bit signal (e) to the main signal (a) for simplifying the constitution of the bit error rate monitor circuit, allowing to detect easily the coincidence/dissidence.