Title:
DEVICE FOR COMPUTING VARIOUS SIZES OF DFT
Document Type and Number:
Japanese Patent JP2010016831
Kind Code:
A
Abstract:
To minimize both of complexity and latency by implementing a hardware of general prime factor algorithm (GPFA) on an integrated circuit.
A device is presented, where the device implements discrete Fourier transform (DFT) in a self-aligned type and in-place format for a composite size that can be factorized into products of mutually prime numbers. In this case, some or all of the numbers can be expressed as a power of a given radix. A DFT device can dynamically change the size of DFT between two consecutive transforms. Also, derivations of the above algorithm are presented to further reduce the latency at the sacrifice of an increase in the complexity.
Inventors:
NOURISSON XAVIER
BOUTTIER ARNAUD
BOUTTIER ARNAUD
Application Number:
JP2009160544A
Publication Date:
January 21, 2010
Filing Date:
July 07, 2009
Export Citation:
Assignee:
MITSUBISHI ELEC R&D CT EUROPE
International Classes:
H04J11/00
Attorney, Agent or Firm:
Michiharu Soga
Hidetoshi Furukawa
Suzuki Kenchi
Kajinami order
Masahiro Taguchi
Hidetoshi Furukawa
Suzuki Kenchi
Kajinami order
Masahiro Taguchi