To provide a device and a method for automatically generating a verification program and a property for verifying the design (operation) of a processor.
An automatic verification program generator 1 is composed of an operation model generating part 7 for inputting a processor specification 3 and generating an operation model 5 of the processor, a verification item set generating part 11 for inputting the operation model 5 and the processor specification 3 and generating a verification item set, a verification item set editing part 15 for inputting an existent verification program 13 and the operation model 5 and editing a verification item set 9 and a verification program generating part 19 for inputting the verification item set 9 and the operation model 5 and generating a verification program 17 corresponding to individual verification items.
| JPS6337268 | TESTER OF SEMICONDUCTOR DEVICE |
| JP5326406 | Transmitter |
IMAI HIROSHI
MIZUNO ATSUSHI
KAMIYA HIRONORI
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